1. Field of the Invention
The invention in general relates to the fabrication of integrated circuits and more particularly to an apparatus and method for reducing critical dimension loss during etching at the interface of two materials that belong to the same etch chemistry class.
2. Statement of the Problem
As is well-known, integrated circuits, sometimes called semiconductor devices, are generally mass produced by fabricating hundreds of identical circuit patterns on a single semiconducting wafer, which wafer is subsequently sawed into hundreds of identical dice or chips. While integrated circuits are commonly referred to as "semiconductor devices" they are in fact fabricated from various materials which are either electrically conductive, electrically nonconductive, or electrically semiconductive. Silicon, the most commonly used semiconductor material, can be used in either the single crystal or polycrystalline form. In the integrated circuit fabrication art, polycrystalline silicon is usually called "polysilicon" or simply "poly", and shall be referred to as such herein. Both forms of silicon may be made conductive by adding impurities to it, which is commonly referred to as "doping". If the doping is with an element such as boron which has one less valence electron than silicon, electron "holes" become the dominant charge carrier and the doped silicon is referred to as P-type silicon. If the doping is with an element such as phosphorus which has one more valence electron than silicon, additional electrons become the dominant charge carriers and the doped silicon is referred to as N-type silicon. Silicon dioxide is also commonly used in integrated circuits as an insulator or dielectric. Its use is so common that in the art is generally referred to as "oxide" without ambiguity.
Integrated circuit fabrication may begin with a lightly-doped P-type silicon substrate, a lightly-doped N-type silicon substrate, or lightly-doped epitaxial silicon (deposited crystalline silicon) on a heavily doped substrate. For the sake of simplicity, the invention will be described using lightly-doped P-type silicon as the starting material, although it may be implemented with other materials as the starting point. If other materials are used as the starting point, there may be differences in materials and structure as is well-known in the art, e.g. with N-type silicon as the starting point dopant types may be reversed, or P-type wells may be introduced.
An integrated circuit will generally have areas of electrical activity, referred to as active areas or AA's, separated by silicon oxide insulating areas, generally referred to as field oxide regions. In the fabrication of many integrated circuit devices, such as memory arrays, a thin protective layer of silicon dioxide, called the pad oxide, is formed on the surface of the substrate, then the field oxide regions are formed to electrically isolate the future active areas from one another.
The process of defining the AA's and forming the field oxide regions has developed into a specialized technology sometimes referred to as LOCOS (LOCalized Oxidation of Silicon). The LOCOS technology comprises depositing a silicon nitride layer over the pad oxide, then using a mask and etch process to define the AA's. This mask and etch process is a well-known semiconductor fabrication process involving the following steps: a photo mask containing the pattern of the AA's to be fabricated is created; the silicon nitride layer is coated with a light-sensitive material called photoresist or resist; the resist-coated wafer is exposed to ultraviolet light through the mask to soften or harden parts of the resist depending on whether positive or negative resist is used; the softened parts of the resist are removed; the silicon nitride is etched to remove the part unprotected by the resist; and the remaining resist is stripped. The silicon nitride remaining after this process defines and protects the AA's from being oxidized during the formation of the field oxide regions.
The step of etching the silicon nitride presents serious technical problems in the standard LOCOS process. In etching the silicon nitride, it is important that the etch stops on the pad oxide layer, otherwise the silicon substrate below may be damaged. However, silicon nitride and silicon oxide are in the same etch chemistry class; i.e each are etchable by the same basic chemistry, e.g. fluorine chemistry is generally used to etch the silicon nitride. The conventional solution to this problem is to add large amounts of oxygen to the etch. The more oxygen in the etch, the more selective the etch is to silicon oxide. Here, the word "selective" means that the etch does not etch the silicon oxide but rather stops on the oxide. However, this results in a further problem. The use of large amounts of oxygen in the nitride etch process results in very rapid isotropic removal rate of the photoresist mask layer. As the resist mask is laterally etched, it exposes more and more of the silicon nitride. See FIG. 1. This results in critical dimension loss, often referred to as CD loss. That is, the critical dimension, the width X of the gap defined by the resist layer is lost. This CD loss can amount to 0.1 to 0.15 microns.
The advantages of building integrated circuits with smaller individual circuit elements so that more and more circuitry may be packed on a single chip are well-known: electronic equipment becomes less bulky, reliability is improved by reducing the number of solder or plug connections, assembly and packaging costs are minimized, and improved circuit performance, in particular higher clock speed, is achieved. However, the smaller the size, of the individual circuit elements, the more significant that CD loss becomes. In the current generation of DRAM under development, 64 MBit DRAM, the density has become such that the CD loss in the nitride etch process has become a very significant problem leading to defective devices. Thus there is a need for an etch process that minimizes or does not produce CD loss during etching at the interface of two materials of the same etch class, as in the etch of silicon nitride at an oxide interface.
It has been discovered, which discovery is part of the invention to be described below, that the CD loss can be minimized by a known process, called the poly buffered LOCOS (PBL) process. The PBL process addresses a problem that develops in the above-described LOCOS process, caused by the fact that the pad oxide is reactive in the field oxide formation process and can permit encroachment of field oxide under the nitride layer and into the AA. The thinner the pad oxide, the less this encroachment. However, the pad oxide is subject to stresses from the nitride layer, and if it is made too thin, the high stress level can result in significant damage to the silicon substrate beneath. In the PBL variation of the LOCOS process a polysilicon film is deposited between the pad oxide and the silicon nitride depositions. See U.S. Pat. No. 4,541,167 issued to Robert H. Havemann. The poly film reduces stress between the oxide and the silicon nitride, permitting a thinner pad oxide layer and thus reducing encroachment of the field oxide into the AA's. As described in U.S. Pat. No. 4,541,167, referred to above, the polysilicon film in the PBL process must be at least 500 .ANG. thick, otherwise it will not be sufficient to provide the stress-relief function. However, such a thick polysilicon layer, requires considerable etching to remove after the field oxide layers are created. Further, since polysilicon is a common material used in integrated device structures, etching of such a thick layer of polysilicon requires careful attention to the design of the fabrication process so that desired polysilicon is not etched. Further, in many integrated circuit designs, especially in the very dense circuits, the CD loss problem is much more significant than the encroachment problem. Thus there is a need for a process that solves the CD loss problem, but does not use large thicknesses of polysilicon under the nitride.